Introduction to Digital Circuit Design

Logic states are electrically represented by 2 voltage levels. For TTL, these voltage levels are approximately 5V and 0V.

There are two representation conventions: positive logic and negative logic.

In positive logic, 5V is logic 1 and 0V is logic 0. In negative logic, the inverse is true; 5V is logic 0 and 0V is logic 1. In this strand, we tend to use the positive logic convention. Voltages are in respect to earth. High is considered to be logic 1 and low is logic 0.

AND

OR

NOT

Three-input gates

NAND

NOR

XOR

NOT

AND

OR

AND

OR

NOT

A + B = B + A
A.B = B.A

A + B + C = A + (B + C) = (A + B) + C
A.B.C = A.(B.C) = (A.B).C

A + B = A.B
A.B = A + B

A.(B + C)
= A.B + A.C

(A + B).(C + D)
= A.C + B.C + B.D + A.D

A.B + A.B
= A.(B + B)
= A

A.(A + B)
= A + A.B
= A.(1 + B)
= A

C = A.B + A.B

Y.Z = Y + Z

A single variable or logical product of several variables. E.g., A, X, A.B.C. This is basically the AND function. Note that A.B.C is not a product term.

Sum term is the single variable or the logical sum of several variables. The variables may be in true, or complemented, form. E.g., A + B + C, etc... This is the OR function. Note that here also, A + B + C is not a sum term.

This is product terms added together., e.g., A.B.C + Q.R.S + A.Q. Note that A.B.C + X.Y.C is not a valid sum-of-products form.

This is the sum of several terms multiplied together, e.g., (A + B + C).(X + H + J). Note that (A + B + C).(C + D) is not in product of sums form.

The first canonical form

The second canonical form

Minterm

Maxterm

These are the biggest adjacent terms which can be looped together. Single isolated implicants are also prime implicants.

This is a prime implicant that contains a minterm not included in any other prime implicants. Isolated minterms are also essential prime implicants. An essential prime implicant must be included in the final expression.

This can be used when you nearly have a minterm, but there is one maxterm blocking it. If you realise a design assuming that the maxterm is indeed a minterm (and you then have a prime implicant) you can then add in an inhibiting function which stops the circuit being true unless the maxterm is false, making your assumption work as intended.

However, this increases gate delay, but does tend to lead to fewer gates or packages being used. It can also make it less obvious what a design is for.

You need to treat each circuit as if it were being generated by an independent circuit and look for common terms.

Don't cares are input conditions that will never occur under normal operations and are marked as output X. You can treat a don't care as either a max-term or a min-term, whichever is more convenient for you. So, for example, you can loop a don't care with minterms or maxterms to create a more minimised expression. Don't cares by themselves are not looped however.

You need to take care, however, incase a don't care term does occur (for example during the initialisation of flip-flops, etc).

Which hardware implementation to use? PCB, IC, PLD? Which device technology? TTL, CMOS transistors, ECL? Hardware environment? Temperature, radiation, pressure, vibrations, etc...

You need to minimise gates and packages, the gate layers (circuit delay), the number of interconnects between gates and between packages, maintenance costs, power consumption, weight, design costs, production costs, hazardous behaviour.

Check each stem!

1. Obtain requirements - an imprecise statement of objectives
2. Map requirements into a formal specification - truth table, etc
3. Design the circuit - use minimisation
4. Realise the circuit - consider any further minimisation
5. Analyse the circuit - either by hand or on computer. Allow for production and environmental consideration.
6. Prototype the circuit - check it on the lab under full range of conditions
7. Test

Temperature ranges: Standard: 0 °C - 70 °C; Military -55 °C - 125 °C

Gates are supplied by power from a power supply via a power rail known as V_cc and ground. This power rail is implied and not actually show on circuit diagrams. In a dual-inline package, powering the package automatically powers all the gates.

Normally, the power supply is 5 V. For standard specification gates, the allowed variances are ±0.25 V and for military this is ±0.5 V. There is also an absolute voltage rating, above which the gate burns out. This is approximately 7 V.

Output is high when Q1 is on and Q2 is off, inversely, output is low when Q1 is off and Q2 is on. During transitions, Q1 and Q2 both conduct, but current is limited by R1, this causes a "spike" to be seen on the supply rail and is known as electrical noise. The spike is caused by the sudden increase and then decrease in current required by the gate. Capacitors are evenly spread around a PCB according to some in-house rule of thumb. These "decoupling" capacitors are connected between supply rail and earth, supplying instantaneous current which the transistors need.

When the interconnecting node is low, current flows out of the second gate into the first one. The inverse happens when the interconnect is high.

In a data book, the following notations are used to signify currents:

• I_OL - output when low
• I_OH - output when high
• I_IL - input when low
• I_IH - input when high

NAND and NOR gates can be used as inverters. 4-input gates can be used by 2 variables only, etc... However, TTL inputs float high and CMOS floats low. For a TTL 4-input AND: ABC1 = ABC, but for a 4-input OR: A + B + C + 1 = 1, which is a tautology.

Unused inputs are susceptible to electrical noise and may slow down gate operation.

This is two different ways to make a 3-input gate work with two inputs (generating logic 0). The bottom method is preferred.

To generate logic 1, you can do something like this:

The bottom circuit can only be used with low-power Schottky, however. For other devices, you can tie them to the Vcc rail using a 1k Ω resistor.

SSI - small scale integration. 1 - 20 gates, up to 100 transistors, few gates and flip flops.

MSI - medium scale integration. 20 - 200 gates, functional building blocks.

LSI - large scale integration. 200 - 200,000 gates, PLDs and early microprocessors.

VLSI - very large scale integration. 500,000+ gates, 32-bit microprocessors, etc...

The propagation delay of a gate is the time it takes for the gate output to change in response to a change on its input. High-to-low delays may differ from low-high-delays.

t_PHL is the time between specified reference points on the input and output voltage waveforms with the output changing from the defined high level to the defined low level.

t_PLH is time between specified reference points on the input and output voltage waveforms with the output changing from the defined low level to the defined high level.

A static hazard is where there's a change from minterm to minterm (static-1) or maxterm to maxterm (static-0) and a "blip" occurs. A dynamic hazard is where there's a hazard in a change between max- and min-terms.

Buffers help mask propagation delays and can decrease hazards. This, however, isn't the best solution to hazards. Waveform analysis is a better indicator for predicting hazards, but it may not be accurate in reality.

This standard defines a bus standard. There are 86 wires (16 bit bi-directional data bus, 24 bit address bus, 26 bit control bus (used for data-transfer commands, handshaking, etc) and a 20 bit power and ground line bus (8 GND, 8 +5 V, 2 +12 V, 2 -12 V)).

These type of devices can accept voltages of ±15 V on the Vcc rail, and can therefore sink higher voltages. They are typically indicated by a star over the end of the gate. Because of this, you can do things like this:

The value of R is calculated according to a formula specified by the manufacturer. The value must be re-calculated every time an input or output is added or removed.

Wired-AND Gate

Tristate devices have 3 output states

• TTL logic 1 state
• TTL logic 0 state
• A high-impedance state

A tristate device can sink and drive large currents than TTL.

Of all the gates connected to a bus wire, only one should drive at once. All gates can be in a high impendence state, however.

Representation

Z₀ = v / i

Inverters lead to NAND gates which lead to XOR gates. The XOR inverts. NAND gates and output polarity are programmable. If the polarity of the XOR gate is intact, the NAND gate is shown, otherwise the other input is set to logical 1 and inverted.

This is a programmable AND array, but a fixed OR array. In PALs, every output is not programmable with every possible input combination, however they are low cost and easily programmed. If you have any unused AND gates in the array, all fuses must be intact, which sets the output to 0 which doesn't interfere with the OR.

Some PALs have tristate buffers for bus driving (the tristate selects whether the PAL is an driving or receiving), hence the PAL can be used for inputs and outputs.

This has a programmable AND array and OR array.